Structure of the Instructions of Processors

An instruction to be executed by computer should specify the following:

1.       The task to be carried out by the processor.

2.       The address or addresses in memory where the operand or operands would be found.

3.       The address in memory where the result is to be stored.

4.       The address in memory where the next instruction to be carried out is stored.

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For example, suppose an operand stored in address P in memory is to be added to one stored in Q and the result is to be stored in an address R, and the address of the next instructions to be executed in s, then an instruction would be of the following type:

Add	P	Q	R	S
What task? (Operation code)	Address of the First operand	Address of the second operand	Address of the result	Address where the next instruction would be found

 The instruction given above is known as a four- address- instruction. If a memory has 256K addresses, then each address would be 18 bits long. Four addresses would require to store a four address instruction would be quite large. Many instructions, however, would not require all the addresses. Normally in an algorithm, Instructions are carried out sequentially, that is, one after another. If an instruction is stored in an address X, then the next instruction would be stored in the next consecutive address, namely, X+1. Only on rare occasions is the normal sequence violated and the program jumps to a specified address. Thus, the fourth address, S, need not be explicitly specified in each instruction. If we remove the fourth address, we get a three address instruction. Three addresses will require 54 bits to specify if the memory has 256K addresses. This instruction length is also too long. Again, however, many instructions would not require all three addresses. For example, an instruction to change the sign of a number stored in memory would need only the address of the number. In order to simplify the design of processors, it would be preferable to have a uniform size for all instructions. If it is decided to use only one address in each instruction, the processor design will be simplified. We would, however, need a register in the processor where an operand may be stored and whose address need not be explicitly specified but will be implied in various operations. One such register is known as accumulator register. If a processor has an accumulator, then an instruction to ADD given easier may be reformulated as a series of three instructions:

1.       Clear the accumulator register in the processor and place the first operand from address P in it.

2.       Add to the accumulator register the operand stored in Q and leave the result in the accumulator.

3.       Store the contents of the accumulator in address R of memory.

These instructions are summarized as the three single - address instructions shown in table1. It should be clearly understood while writing a program that when we say ADD Q; we do not mean add the number Q. We mean add the stored in memory in address Q. The availability of an accumulator in a processor allows intermediate results to be kept in it and subsequently used without unnecessarily storing it in the memory and retrieving it from the memory. As an example, a series of instructions to read a set of numbers, add them and print the result are given in following table2. Observe that the intermediate results remain in the accumulator and are used subsequently. Observe the column labeled ‘instruction address’ in the program of table 2.Each instruction in the program is also stored in memory. The address where the first instruction of the above program is stored is X. The second instruction is stored in the next address X+1. Succeeding instructions are stored in successive address. The notable C (K) in Table 2 means contents of address K in memory. Content of the accumulator is abbreviated as ACC in this table.

What task? (Operation)	Address of operand	Abbreviated instruction
Clear accumulator and place operand in it	P	CLA P
Add operand to accumulator	Q	Add Q
Store the content of the accumulator in R	R	STO R

                                          Table1 A Sequence of single- address instructions

In a processor, a string of bits is used to code the instructions. Addresses are also binary numbers. If a processor has 16 different operations, 4 bits would be needed to represent each operation. If the memory size 4K words, then 12 bits are needed to represent each address. The format of a typical instruction is shown in Figure 1. Using the operation codes given in table 3, the program of table 2 would be as shown in table 4. The program is stored from the address (008) hex. Hexadecimal notation is used for conciseness. The term ‘address’ used in the preceding discussions refers to the address of an operand. The length of the operand (number of bits in it) is not specified. If we assume that the length of an operand equals the length of an instruction, then the instruction and the operand are said to occupy one word in a computer’s memory. If the smallest addressable unit in a computer is a word, then such a computer is known as a word addressable computer. A computer in which each byte stored can be addressed individually is known as a byte addressable computer. The program given in Table 4 is known as machine language program. Observe that the instructions are stored in the memory beginning from address 008 up to address 012. Data to be processed is also stored in the same memory from address 200 up to 204. It is the responsibility of the mac               

Address where instruction is stored in memory	Operation	Operand address	Remarks
X	READ	K	Read n1 from the input unit and store it in k
X+1	READ	L	Read n2 from the input unit and store it in L
X+2	READ	M	Read n3 from the input unit and store it in M
X+3	READ	N	Read n4 from the input unit and store it in N
X+4	CLA	K	Move C (K) – n1 to the accumulator
X+5	ADD	L	ACC <- ACC + C (L) =n1+n2
X+6	ADD	M	ACC<- ACC+ C (M) = n1+n2+n3
X+7	ADD	N	ACC<- ACC+ C (N) = n1+n2+n3+n4
X+8	STO	W	C (w ) <-ACC=n1+n2+n3+n4
X+9	PRINT	W	Print C (W) =n1+n2+n3+n4
X+10	HALT

                                     Table 2 A program to add a set of numbers

Operation Code

Operand address

   |<-             4 bits         ->                      |       <-                  12 bits            ->                                           |                                 Figure 1 Format of a single-address instruction.

       

Operations	Operation code (in binary)	Operation ode (In hexadecimal)
READ	1010	A
CLA	0001	1
ADD	0010	2
STO	0110	6
PRINT	1011	B
HALT	1111	F

                   Table 3 Binary and hexadecimal codes for operations

Instruction address (hexadecimal)	Instruction			Remarks
	Operation Code		Operand address
008	A	200		Read n1 and store it in 200
009	A	201		Read n2 and store it in 201
00A	A	202		Read n3 and store it in 202
00B	A	203		Read n4 and store it in 203
00C	1	200		Accumulator <- C (200)= n1
00D	2	201		ACC <- ACC+C (201)= n1+n2
00E	2	202		ACC <- ACC + C (202)=n1+n2+n3
00F	2	203		ACC <- ACC+ C (203)=n1+n2+n3+n4
010	6	204		C (204) <- ACC= n1+n2+n3+n4
011	B	204		Print C (204)= n1+n2+n3+n4
002	F			Halt

          Table 4 Machine language program corresponding to the program of table 2

Language programmers to ensure that the program area and data area in memory are kept separate and  is not accidently over an instruction is not accidentally written over data.